The present invention relates to a process for manufacturing a semiconductor wafer, a semiconductor wafer, a process for manufacturing a semiconductor integrated circuit device, and a semiconductor integrated circuit device and, more particularly, to a technique which is effective if applied to the so-called xe2x80x9cepitaxial wafer manufacturing processxe2x80x9d for forming an epitaxial layer over the surface of a semiconductor substrate body, an epitaxial wafer, a process for manufacturing a semiconductor integrated circuit device by using the epitaxial wafer, and a semiconductor integrated circuit device.
The epitaxial wafer is a semiconductor wafer which is formed with an epitaxial layer over the principal surface of a mirror-finished (or -polished) semiconductor mirror wafer (or polished wafer) by the epitaxial growth method. Incidentally, the epitaxial growth method is described, for example, on pp. 51 to 74 of xe2x80x9cVLSI TECHNOLOGYxe2x80x9d, edited by S. M. Sze and issued in 1983 by McGraw-Hill. On the other hand, the polishing is described on pp. 39 to 42 of the same Publication, for example.
The epitaxial wafer is featured in that it is excellent in suppressing the soft errors and resisting to the latchup, and in that the gate insulating film to be formed over the epitaxial layer can have excellent breakdown characteristics to drastically reduce the defect density of the gate insulating film. Thus, there has been promoted the application of the epitaxial wafer to the technique for manufacturing the semiconductor integrated circuit device.
As to this epitaxial wafer, there are the following two techniques.
The first technique is described on pp. 761 to 763 of xe2x80x9cApplied Physics, Vol. 60, No. 8xe2x80x9d, issued on Aug. 10, 1991 by Japanese Association of Applied Physics. There is described an epitaxial wafer, in which a p+-type (or n+-type) semiconductor substrate is formed thereover with a p- (or n-) type epitaxial layer containing a p- (or n-) type impurity having a lower concentration than the p- (or n-) type impurity concentration of the semiconductor substrate.
In this case, there is described the structure in which a semiconductor region called the xe2x80x9cwellxe2x80x9d is formed in the epitaxial layer and is formed thereover with a MOS.FET. Since the well of this case is formed by the diffusion of the impurity from the surface of the epitaxial layer, the impurity concentration in the well is distributed to be high in the surface and low in its inside.
The second technique is described in Japanese Patent Laid-Open No. 260832/1989, for example and is directed to an epitaxial wafer which has a p-type epitaxial layer over a p-type semiconductor substrate. In this case, an element forming diffusion layer is formed to extend from the surface of the epitaxial layer to the upper portion of the semiconductor substrate.
Also described is a process, in which the semiconductor substrate body is doped at the time of forming the diffusion layer with a diffusion layer forming impurity so that simultaneously with the growth of the epitaxial layer over the semiconductor substrate body, the impurity in the upper portion of the semiconductor substrate body may be diffused to form the diffusion layer.
The distribution of the impurity concentration of this case is made to have such a plateau curve having a peak at the boundary between the epitaxial layer and the semiconductor substrate body that the impurity concentration is low at the surface side of the epitaxial layer, high at the boundary between the epitaxial layer and the semiconductor substrate body and low in the semiconductor substrate body.
However, the semiconductor integrated circuit device manufactured according to the aforementioned first technique is excellent in the performance and reliability but has a problem in the cost because the semiconductor substrate used contains a (p+-type or n+-type) impurity in a high concentration and is expensive and because an epitaxial layer having a large thickness is formed over the semiconductor substrate.
According to the aforementioned second technique, on the other hand, the diffusion layer is formed by the so-called xe2x80x9cupper diffusionxe2x80x9d to diffuse the impurity in the upper portion of the semiconductor substrate. As a result, the impurity concentration is so difficult to set that there arise a problem that the diffusion layer forming accuracy drops. Another problem is that it is obliged to change the LSI (i.e., Large Scale Integration circuit) manufacturing process using the so-called xe2x80x9cmirror waferxe2x80x9d.
An object of the present invention is to provide a technique capable of the cost for a semiconductor wafer having a semiconductor single crystal layer over a semiconductor substrate.
Another object of the present invention is to provide a technique capable of improving the performance and reliability of a semiconductor integrated circuit device and reducing the cost for the semiconductor integrated circuit device.
An object of the present invention is to provide a technique capable of facilitating the control of forming a semiconductor region on the semiconductor wafer which has the semiconductor single crystal layer over the semiconductor substrate.
An object of the present invention is to provide a technique capable of using a process for manufacturing the semiconductor integrated circuit device using the so-called xe2x80x9cmirror waferxe2x80x9d, as it is.
The aforementioned and other objects and the novel features of the present invention will become apparent from the following description to be made with reference to the accompanying drawings.
Representatives of the invention disclosed herein will be briefly described in the following.
Specifically, according to the present invention, there is provided a process for manufacturing a semiconductor wafer, comprising the step of forming such a semiconductor single crystal layer over the surface of a relatively lightly doped semiconductor substrate body, which contains an impurity of a predetermined conduction type, as contains an impurity having the same conduction type as that of said impurity and the same concentration as the designed one of said impurity.
Moreover, according to the present invention, there is provided a process for manufacturing a semiconductor integrated circuit device, comprising: the step of preparing a relatively lightly doped semiconductor substrate body, which contains an impurity of a predetermined conduction type and which is formed over the surface of a semiconductor single crystal layer containing an impurity having the same conduction type as that of said impurity and the same concentration as the designed one of said impurity; and the step of forming an oxide film over said semiconductor single crystal layer.
Moreover, according to the present invention, there is provided a process for manufacturing a semiconductor integrated circuit device, comprising: the step of preparing a relatively lightly doped semiconductor substrate body, which contains an impurity of a predetermined conduction type and which is formed over the surface of a semiconductor single crystal layer containing an impurity having the same conduction type as that of said impurity and a concentration not higher than that of said semiconductor substrate body; the step of forming a first semiconductor region extending from the surface of said semiconductor single crystal layer to the upper portion of said semiconductor substrate body and having the same conduction type as that of said impurity and its impurity concentration gradually lowered depthwise of said semiconductor single crystal layer; and the step of forming an oxide film over said semiconductor region.
Moreover, according to the present invention, there is provided a semiconductor integrated circuit device manufacturing method comprising the step of doping said semiconductor single crystal layer with the ions an impurity and then thermally diffusing said impurity, at the step of forming said first semiconductor region.
Moreover, according to the present invention, there is provided a semiconductor integrated circuit device manufacturing method characterized in that said first semiconductor region is a well to be used for forming a complementary MOSxc2x7FET (Metal-Oxide-Semiconductorxc2x7Field-Effect-Transistor) circuit (i.e., for forming a complementary MIS (Metal-Insulator-Semiconductor)xc2x7FET circuit).
According to the aforementioned semiconductor wafer manufacturing process of the present invention, any semiconductor substrate body of high price and density (of p+- or n+-type) need not be used, and the semiconductor single crystal layer can be thinned, so that the cost for the semiconductor wafer capable of realizing high element characteristics and reliability can be lowered.
According to the aforementioned semiconductor integrated circuit device manufacturing process of the present invention, moreover, a gate insulating film having an excellent film quality can be formed by forming the gate insulating film of a MOSxc2x7FET over a semiconductor single crystal layer so that the gate insulating film can have its breakdown voltage raised to reduce the defect density of the gate insulating film. Moreover, the semiconductor substrate body of high price and density need not be used, but the semiconductor single crystal layer can be thinned to reduce the cost for the semiconductor integrated circuit device having high element characteristics and reliability.
According to the aforementioned semiconductor integrated circuit device manufacturing process of the present invention, moreover, the degree of freedom for setting the impurity concentration and depth is so high when a semiconductor region such as a well is formed in the semiconductor substrate, as to facilitate the control of the formation. As a result, it is possible to reduce the defective products thereby to improve the production yield. Moreover, the cost for the semiconductor integrated circuit device can be lowered.
According to the aforementioned semiconductor integrated circuit device manufacturing process of the present invention, moreover, the impurity concentration of the semiconductor substrate body below the semiconductor single crystal layer is made higher than that of the semiconductor single crystal layer, so that the resistance of the semiconductor substrate body can be relatively lowered to improve the resistance to the latchup.
According to the aforementioned semiconductor integrated circuit device manufacturing process of the present invention, moreover, since the first semiconductor region is formed by the ion implantation method and the thermal diffusion method, the semiconductor integrated circuit device can be manufactured without being accompanied by any change in the design or manufacture process but by using the same method as that of the semiconductor integrated circuit device having the so-called xe2x80x9cmirror waferxe2x80x9d, when it is to be manufactured by using the semiconductor wafer having the semiconductor single crystal layer over the semiconductor substrate body.
According to the aforementioned semiconductor integrated circuit device manufacturing process of the present invention, moreover, since the memory cell of the dynamic type random access memory is formed over the semiconductor single crystal layer having less defects such as the precipitation of oxygen, it is possible to reduce the junction leakage current in the source region and the drain region of the transfer MOSxc2x7FET of the memory cell. Since, moreover, the charge leakage in the capacitor of the memory cell can be suppressed to elongate the charge storage time period, it is possible to improve the refresh characteristics. As a result, it is possible to improve the performance, reliability and production yield of the dynamic type random access memory.
According to the aforementioned semiconductor integrated circuit device manufacturing process of the present invention, moreover, since the memory cell of the static type random access memory is formed over the semiconductor single crystal layer having less defects such as the precipitation of oxygen, the junction leakage current of the source region and drain region of the MOS. FET composing the memory cell can be reduced to improve the data retention level thereby to reduce the data retention fault percentage. As a result, it is possible to improve the performance, reliability and production yield of the static type random access memory.
According to the aforementioned semiconductor integrated circuit device manufacturing process of the present invention, moreover, the memory cell of a read only memory capable of electrically erasing and programming data is formed over the semiconductor single crystal layer having less defects such as the precipitation of oxygen, so that the resistance to the data programming can be improved and so that the dispersion of the data erasure can be reduced. As a result, it is possible to improve the performance, reliability and production yield of the read only memory capable of electrically erasing and programming the data.